Verilog digital system design: RT level synthesis, testbench and verification

Navabi, Zainalabedin

Verilog digital system design: RT level synthesis, testbench and verification Zainalabedin Navabi - 2nd - New Delhi McGraw Hill Education (India) 2014 - xvi, 344+One CD-ROM

Includes bibliographical references and index

9780070252219


Digital electronics-computer aided design
Logic Circuits-Computer aided design

621.395 / NAV P14

Powered by Koha