Transistor level modeling for Analog/RFIC design (Record no. 21107)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 00338 a2200121 4500 |
| 000 - LEADER | |
| fixed length control field | nam a22 7a 4500 |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Grabinski, Wladyslaw |
| 110 ## - MAIN ENTRY--CORPORATE NAME | |
| Corporate name or jurisdiction name as entry element | Grabinski, Wladyslaw |
| 245 ## - TITLE STATEMENT | |
| Title | Transistor level modeling for Analog/RFIC design |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. | |
| Name of publisher, distributor, etc. | Springer Nature link |
| Date of publication, distribution, etc. | 2006 |
| 264 ## - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE | |
| Name of producer, publisher, distributor, manufacturer | Springer Nature link |
| Date of production, publication, distribution, manufacture, or copyright notice | 2006 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | Books |
No items available.