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Verilog digital system design: RT level synthesis, testbench and verification Zainalabedin Navabi
Material type:
TextLanguage: English Publication details: New Delhi McGraw Hill Education (India) 2014Edition: 2ndDescription: xvi, 344+One CD-ROMISBN: - 9780070252219
- 621.395 NAV P14
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Deen Dayal Upadhyaya College Library | 621.395 NAV P14 (Browse shelf(Opens below)) | Available | 5 BC 27.4 | 44022 | |
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Deen Dayal Upadhyaya College Library | 621.395 NAV P14 (Browse shelf(Opens below)) | Available | SC 307 | 44023 | |
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Books
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Deen Dayal Upadhyaya College Library | 621.395 NAV P14 (Browse shelf(Opens below)) | Available | SC 307 | 44024 |
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| 621.395 MAR P2 Introduction to logic design | 621.395 MON P17 Programming FPGAS: getting started with Verilog | 621.395 NAV P14 Verilog digital system design: RT level synthesis, testbench and verification | 621.395 NAV P14 Verilog digital system design: RT level synthesis, testbench and verification | 621.395 NAV P14 Verilog digital system design: RT level synthesis, testbench and verification | 621.395 PAD P17 Design through Verilog HDL | 621.395 PAD P17 Design through Verilog HDL |
Includes bibliographical references and index
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