Padmanabhan, T.R. <br/><br/>
Design through Verilog HDL 
T.R. Padmanabhan 
 - Wiley  student 
 - Hoboken, NJ; New Delhi  John Wiley; Wiley India [Printer]  2017 
 - xii, 455 
<br/><br/> Includes bibliographical references and index 
<br/><br/><label>ISBN: </label>9788126519316 
<br/><br/><label>Subjects--Topical Terms: </label><br/>Digital electronics-Computer aided design<br/>Logic Circuits-Computer aided design
<br/><br/><label>Dewey Class. No.: </label>621.395  / PAD P17